Single stage RISC Processor design

RISC Simulatuon Environment

Single stage RISC Processor Diagram

The resulting single cycle RISC processor can handle 12 instruction sets. They are NOP, CPR, AND, NOT, RDM, WRM, ADD, SUB, JMP, JMZ, LPC, LDR. A simple program is tested on this processor successfully with the instructions loaded into the instruction memory.